1. Technical Field
The present invention relates generally to an improved data processing system, and in particular to a method and system for managing data within a data processing system. More particularly, the present invention relates to the field of clock/data recovery for self-clocked high speed interconnects.
2. Description of Related Art
Interconnect effects are critically important in the design and verification of integrated circuits. On-chip interconnects are typically modeled by linear resistive (R) and capacitive (C) elements. With the scaling of the Back-End-Of-the-Line (BEOL) interconnect processes, the effect of interconnect on circuit performance continues to increase. In case of global nets (i.e., nets connecting one macro to another macro), the interconnect delay may typically be much greater than the logic delay. Even among nets within a macro the interconnect delay may constitute a significant portion of the path delay (i.e., typically up to 25%).
High speed interconnections between processors or switch elements are one of the main bottlenecks to system performance today as system bandwidth requirements grow geometrically. Many factors contribute to this problem, for example, chip and packaging density, power dissipation, logic switching speeds, available low-noise analog circuit technologies, and the like. As speeds increase the nonlinear loss mechanisms through the channel require more precise detection techniques involving sensitive analog circuits, such as phase-locked loops (PLLs), for recovery of the timing information and sampling of the data stream.
A PLL integrated in a mixed-signal environment containing other PLLs and many noise-producing digital circuits may have unpredictable degradation on performance. For example, a PLL integrated in a mixed-signal environment containing other PLLs may force fundamental or harmonic false-locking due to injection or other effects. In addition, bandwidth-preserving transmission such as non-return-to-zero (NRZ) with some form of run-length-limitation requires advanced clock recovery techniques due to low transition density and no component at the clock frequency.
With Manchester data transmission, a serial data stream contains both the clock and the data, with the position of the mid-bit transition representing the clock, and the direction of the transition representing the data. Manchester has bandwidth, error detection, and synchronization advantages over NRZ code. However, presently available Manchester clock and recovery systems use precise delay lines or one-shots which are difficult to integrate precisely using existing CMOS process technology.
Thus, it would be advantageous to have an improved method and system for clock/data recovery for self-clocked high speed interconnects.